The present invention relates generally to a circuit for selecting a sequence of elements. More particularly, the present invention relates to a programmable circuit for selecting a repeatable sequence of elements at a high speed.
In a data processing system the performance of the central processing units (CPUs) is often limited by their data-storage subsystems. In particular, secondary storage devices used in such subsystems often are incapable of transferring data at a rate that matches the speed with which the CPUs and the system busses are capable of handling the data. To improve the data transfer rate of the data-storage subsystems, and to enhance the overall data throughput of data processing systems, a storage subsystem architecture can be used in which the data is stored in an array of multiple storage devices.
Such a storage array architecture can be implemented by coupling a high-speed data path (e.g., and input/output bus of a CPU) to an array of slower storage devices (e.g., tape or disk drives) via a corresponding array of high-speed memory elements. To write data to the storage devices, the data is divided into segments, and the segments are transferred at high speed one after another over the data path of different ones of the memory elements of the memory element array, which in turn hold the data segments until the corresponding storage devices are ready to receive the data. The segments of data can then be transferred in parallel to the storage devices, such that the entire data may be stored in the storage device array in a shorter time, and with less sacrifice of CPU and system bus cycles, than would be required by a single storage device. The throughout of the high-speed data path is thus enhanced. The stored data can likewise be read from the storage devices at a high speed by transferring segments of data to corresponding memory elements, which in turn transfer one segment after another over the high-speed data path at a rapid rate.
Generally, the known method for directing data into and out of a series of memory elements is to use a state machine sequencer implemented in hardware logic to control a memory element access sequence. This method has several drawbacks. For example, the configuration in which data segments are stored in an array may vary from data transfer to data transfer, thus making it necessary that the sequence in which the data segments are transferred between the data path interface and the storage device array be variable. A state machine sequencer typically lacks sufficient flexibility to accommodate many different data storage configurations, and may require expensive modification to accommodate even a slight change in configuration. This may limit the usefulness of the entire secondary storage subsystem. Known state machine sequencers also are typically complex and expensive. Thus there is a need for a process for selecting memory elements that can be varied to accommodate a wide variety of data storage configurations and that can be implemented in a simple and inexpensive manner.